发明名称 CLOCK GENERATION APPARATUS
摘要 <P>PROBLEM TO BE SOLVED: To provide bust lock clocks and line-locked clocks matched with respective signals without increasing the number of PLLs even when a plurality of different image signals are inputted. <P>SOLUTION: The clock generation apparatus, which is provided with a frequency phase computing circuit 120, simultaneously generates not only a clock synchronizing with a burst lock from a DTO 10 based on frequency information from the DTO 10 and phase error information from a phase comparator 7 and a digital LPF 8 but also a line-locked clock from a DTO 121 and can cope with a system requiring a plurality of clocks. Since frequency diffusion is easily performed by creating diffusion information in a frequency diffusion information generation circuit 90 and adding the diffusion information by the DTO 121, the interference of clocks to a video terminal is reduced and the performance of the video terminal such as a television receiver is taken out. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006115113(A) 申请公布日期 2006.04.27
申请号 JP20040299127 申请日期 2004.10.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SONOBE HIROYUKI
分类号 H04N9/44;H03L7/08;H03L7/087 主分类号 H04N9/44
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