| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a scanning test circuit and a scanning test method capable of shortening a clock cycle. <P>SOLUTION: This circuit comprises the first and second flip-flops FF1, FF2 of a scanning type for taking synchronously either signal of data input terminals D1, D2 and a serial input terminal Sin into a clock to be applied to a clock terminal ck and storing it, and outputting stored either signal from data output terminals Q1, Q2 and a serial output terminal Sout; and a serial output control circuit 16 having an exclusive OR circuit 14 for outputting an exclusive OR of the signal stored in the first and second flip-flops FF1, FF2 and a selector circuit 15 for selecting either signal of outputs from the serial output terminal Sout of the first flip-flop FF1 and the exclusive OR circuit 14. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
