MULTI-STAGE PROGRAMMABLE JOHNSON COUNTER

摘要

A counter has selectable divide factors using multiple multiplexers. The counter includes an inverter and cascading delay stages having selectable stage delays. The inverter connects a stage output of a last one of the delay stages to a stage input of a first one of the delay stages. Each delay stage includes a stage input to receive a quotient signal, at least two paths having different associated path delays each coupled to receive the quotient signal from the stage input, and a multiplexer. The multiplexer is coupled to selectively communicate the quotient signal from one of the at least two paths to a stage output to select one of the stage delays.