发明名称 CLOCK GENERATOR WITH SKEW CONTROL
摘要 Systems and methods are disclosed to provide clock generation. In accordance with one embodiment, a clock generator chip is provided that is configurable and in-system programmable. The clock generator chip may provide programmable input circuits, programmable output circuits, and permit a JTAG boundary scan.
申请公布号 EP1649348(A2) 申请公布日期 2006.04.26
申请号 EP20040757088 申请日期 2004.07.16
申请人 LATTICE SEMICONDUCTOR CORPORATION 发明人 AGRAWAL, OM;KLEIN, HANS;RICKARD, GEOFFREY;WELLER, HARALD
分类号 G06F1/04;G06F1/08;H03L7/18 主分类号 G06F1/04
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