发明名称 |
IMPROVEMENTS IN OR RELATING TO ELECTRONIC CALCULATING MACHINES |
摘要 |
A conversion system for an electronic calculator employs a shift register and a full adder circuit to convert binary digit signals for decimal display purposes. The shift register and full adder include appropriate gating and delay-feedback circuitry for serial conversion, column shift, and read-out. |
申请公布号 |
ZA7008522(B) |
申请公布日期 |
1971.09.29 |
申请号 |
ZA19700008522 |
申请日期 |
1970.12.17 |
申请人 |
OMRON TATEISI ELECTRONICS CO |
发明人 |
YOSIMOTO K;HATANO I;NAGANO A |
分类号 |
G06F7/495;G06F7/50;H03M7/08;H03M7/12 |
主分类号 |
G06F7/495 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|