Non-volatile memory device comprises memory cell including stacked gate structure having floating gate, second insulation layer and first gate electrode, and second and third gate electrode spacers on opposite sidewalls of gate structure

摘要

A non-volatile memory device comprises first and second impurity diffusion regions formed in semiconductor substrate, and a memory cell formed on channel region between impurity diffusion regions. The memory cell comprises a stacked gate structure including floating gate, second insulation layer, and first gate electrode; and second and third gate electrode spacers formed on opposite sidewalls of stacked gate structure and channel region. A non-volatile memory device comprises first and second impurity diffusion regions (123D, 123S) of second conductivity type formed in a semiconductor substrate (101) of first conductivity type; and a memory cell formed on a channel region of semiconductor substrate between the first and second impurity diffusion regions. The memory cell comprises a stacked gate structure (118) including floating gate (113), second insulation layer (115), and first gate electrode which are formed on the channel with a first insulation layer interposed between them; and a second gate electrode spacer disposed adjacent to the first impurity diffusion region and a third gate electrode spacer disposed adjacent to the second impurity diffusion region. The second and third gate electrode spacers are formed on opposite sidewalls of the stacked gate structure and the channel region with a third insulation layer (119) interposed between them. An independent claim is also included for fabrication of non-volatile memory device by preparing a semiconductor substrate; forming a stacked gate structure including floating gate, second insulation layer, and first gate electrode on the substrate, with a first insulation layer interposed between them; forming a second gate electrode spacer and a third gate electrode spacer on opposite sidewalls of the stacked gate structure and the substrate, with a third insulation layer interposed between them to form a memory cell including the stacked gate structure and the second and third electrode spacers on opposite sidewalls of stacked gate structure; and forming a first impurity diffusion region adjacent to the second gate electrode spacer and a second impurity diffusion region adjacent to the third gate electrode spacer at a semiconductor substrate disposed at opposite sides of memory cell.