| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic circuit by which a hold margin can be easily guaranteed, the occurrence of a redundant delay can be prevented, and also, speeding-up and reduction of area can be realized, and to provide a synchronous semiconductor storage device. SOLUTION: The logic circuit has logic blocks 11-1 to 11-4, flip-flop arrays 12-1 to 12-4, formed by arraying a plurality of flip-flops F/F for executing input/output of data of the logic blocks in synchronism with a system clock, and a clock wiring 13, having a trunk line 13-1 and a plurality of branch lines 13-21 to 13-24 and distributing the system clock CLK propagated to the trunk line 13-1 to a plurality of the branch lines 13-21 to 13-24. The flip-flop arrays 12-1 to 12-4 are respectively arranged, corresponding to the arrangement positions (immediately below the branch lines) of the branch lines 13-21 to 13-24 of the clock wiring 13. The corresponding logic blocks 11-1 to 11-4 are arranged to regions other than the arrangement regions of the flip-flop block arrays 12-1 to 12-4. COPYRIGHT: (C)2006,JPO&NCIPI
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