| 摘要 |
PROBLEM TO BE SOLVED: To deter performance reduction of a CPU by an interrupt issued by an accelerator or a DMAC, or poling for deciding processing completion thereof, and to realize a real-time application without interrupting it, in a system wherein a CPU, the accelerator, and the DMAC or the like are bus-connected. SOLUTION: This hardware event handling circuit (module) 40 has: a means connected to an internal bus 20, inputting an interrupt signal from the accelerator or the DMAC 6 as an event; and a means inputting register access via the internal bus 20 as an event. The hardware event handling circuit 40 has the following event states in each the event: (1) a field showing a means generating a new event by combination of the events; (2) a means issuing the interrupt to the CPU with the new event as a trigger; (3) a means accessing the internal bus as a bus master; and (4) a means issuing the interrupt to the CPU at the time point of bus master processing completion. COPYRIGHT: (C)2006,JPO&NCIPI
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