Message passing memory and barrel shifter arrangement in LDPC (Low Density Parity Check) decoder supporting multiple LDPC codes

摘要

Message passing memory and barrel shifter arrangement in LDPC (Low Density Parity Check) decoder supporting multiple LDPC codes. A novel approach is presented by which a barrel shifter may be implemented in conjunction with a single message passing memory within an LDPC decoder. This arrangement also allows for a single bit/check processor to be employed that is operable to perform updating of edge messages with respect to check nodes as well as updating of edge messages with respect to bit nodes. There are a variety of embodiments by which the barrel shifter and the message passing memory may be implemented. By using this approach, a common architecture and design may operate to decode various types of LDPC coded signals including those whose code rate and/or modulation (including constellation shape and mapping) may vary as frequently as on a frame by frame basis or even on a block by block basis.