| 摘要 |
PROBLEM TO BE SOLVED: To provide an output buffer circuit having a pre-emphasis function to reduce the jitter. SOLUTION: The output buffer circuit comprises a first buffer circuit (M1), a second buffer circuit (M2), and first and second capacitors (Z1, Z2). The first buffer circuit (M1) inputs a first logic signal to drive a transmission line (L). The second buffer circuit (M2) serves as a pre-emphasis controller comprising inverted buffers (T4, T5), a first switch (T3) connected between the inverted buffers (T4, T5) and a first power supply (VDD), and a second switch (T6) connected between the inverted buffers (T4, T5) and a second power supply (VSS) and capable of ON/OFF controlling in interlinkage with the first switch (T3). The first and the second capacitors are provided in the circuitry of the input terminal (AA) of the first buffer circuit (M1), and the connecting point between the inverted buffers (T4, T5) in the second buffer circuit (M2) and the first switch (T3); and in the circuitry of the input terminal (AA) of the first buffer circuit and the connecting point between the inverted buffers (T4, T5) and the second switch (AD). COPYRIGHT: (C)2006,JPO&NCIPI
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