CONTROLLING PARASITIC BIPOLAR GAIN IN A CMOS DEVICE

摘要

A CMOS device comprising an n-channel MOS transistor (102) and a p­channel MOS transistor (100), defining a pair of parasitic bipolar transitors (110a, 110b) therebetween, wherein a layer (120) of doped SiGe is provided over the source region (106a) of at least one of the MOS transistors (100, 102), between the source region (106a) and the source contact (122). The layer (120) of material acts as a sink for minority carriers (holes in an N-type device) at the source, which has the effect of increasing surface recombination velocity (because the landgap of SiGe is lower than that of the Si substrate (104)), which, in turn, lowers the current gain of the respective parasitic bipolar device. As a result, the effects and/or occurrence of latch-up, and other breakdown instabilities associated with parasitic bipolar devices, can be limited.