| 摘要 |
A data processor that reduces the chip area of a semiconductor substrate. The data processor includes a detection circuit for generating an error detection code with digital data. A correction circuit generates an error correction code with the digital data that includes the error detection code. A control circuit controls the detection processing circuit and the correction processing circuit in accordance with a control program. The data processor further includes a first external memory and a serial/parallel conversion circuit. The first external memory stores a control program. The serial/parallel conversion circuit receives data of the control program in a serial state from the first external memory and provides a second external memory with the control program data in a parallel state when the data processor is activated.
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