发明名称 ESD protection devices with SCR structures for semiconductor integrated circuits
摘要 To control the uneven distribution of current density and reduce the area of an ESD protection circuit in an SCR-type ESD protection device. An N-type well 11, and P-type wells 12 a and 12 b disposed oppositely and adjacent to the N-type well 11, with the N-type well 11 interposed between them, are formed on the surface of a semiconductor substrate. A high concentration N-type region 15 a is formed on the surface of the P-type well 12 a, a high concentration N-type region 15 b is formed on the surface of the P-type well 12 b, and each of them is grounded. Further, a high concentration P-type region 14 a is formed, oppositely to the high concentration N-type region 15 a, on the surface of the N-type well 11, and a high concentration P-type region 14 b is formed, oppositely to the high concentration N-type region 15 b, on the surface of the N-type well 11, and each of them is connected to an I/O pad. A high concentration N-type region 13 is formed on the N-type well 11, being interposed between the high concentration P-type region 14 a and the high concentration P-type region 14 b, and connected to a trigger device. A surge loaded on the I/O pad is released to the ground terminal via the SCR structures on the both sides.
申请公布号 US2006081935(A1) 申请公布日期 2006.04.20
申请号 US20050250508 申请日期 2005.10.17
申请人 NEC ELECTRONICS CORPORATION 发明人 MORISHITA YASUYUKI
分类号 H01L23/62 主分类号 H01L23/62
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