| 摘要 |
A register circuit includes a passage control circuit and a holding circuit. The passage control circuit includes a first transistor having a gate to which a clock signal is input, a second transistor having a gate to which a data signal is input, and a third transistor having a gate to which a control signal is input, with source-drain paths of the first, second, and third transistors being connected in series. The passage control circuit enables passage of the data signal to the holding circuit according to a state of the clock signal when the control signal is in one of an active state and an inactive state, and disables passage of the data signal to the holding circuit when the control signal is in the other one of the active state and the inactive state. The holding circuit latches the data signal passed from the passage control circuit.
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