METHOD AND DEVICE FOR SEQUENTIAL COMPARISON TYPE AD CONVERSION

摘要

PROBLEM TO BE SOLVED: To shorten conversion cycles of a sequential comparison type AD conversion device with n-bit resolution by using high-order (m) bits of a last conversion result for 3rd continuous conversion and later. SOLUTION: The conversion device is provided with a data register 111 for comparison and a data register 112 for comparison and also provided with a conversion start bit selection register which decides matching bits of a last (i)th (i: not less than 2) conversion result to store high-order (m) bits of the data register 112 for comparison in a predicted data register 114 and determine a conversion start bit for current conversion. A block of them is added to the sequential comparison type AD conversion device to automatically decide the matching high-order (m) bits of the last conversion result and use the high-order (m) bits of the last conversion result, thereby shortening conversion cycles. COPYRIGHT: (C)2006,JPO&NCIPI