发明名称 |
Memory circuit with redundant memory cell array allowing simplified shipment tests and reduced power consumptions |
摘要 |
A memory circuit has a regular memory cell array; a redundant memory cell array that can replace a failed portion in the regular memory cell array; a redundant replacement memory for storing data on the failed portion in the regular memory cell array; and a pre-charge circuit disposed in the regular memory cell array, depending on the data on the failed portion, the failed portion in the regular memory cell array is replaced with the redundant memory cell array, whilst a pre-charge path is closed which leads to the pre-charge circuit corresponding to the failed portion. This enables a common redundant replacement memory to effect a relief of the failed portion and shutoff of the pre-charge current to the failed portion.
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申请公布号 |
US2006083086(A1) |
申请公布日期 |
2006.04.20 |
申请号 |
US20050290506 |
申请日期 |
2005.12.01 |
申请人 |
FUJITSU LIMITED |
发明人 |
TANISHIMA MOTOKO;SAKAKIBARA MITSUHARU |
分类号 |
G01R31/28;G11C29/00;G01R31/3185;G01R31/319;G11C11/413;G11C29/04;G11C29/24;G11C29/50 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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