发明名称 |
Semiconductor memory device |
摘要 |
A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.
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申请公布号 |
US7031199(B2) |
申请公布日期 |
2006.04.18 |
申请号 |
US20040815709 |
申请日期 |
2004.04.02 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
KURODA NAOKI;AGATA MASASHI |
分类号 |
G11C11/34;G11C11/401;G11C7/10;G11C7/22;G11C11/405;G11C11/407;G11C11/409 |
主分类号 |
G11C11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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