System for deriving desired output frequency by successively dividing clock signal frequency by ratios obtained by dividing clock signal frequency by common divisor and specific integer

摘要

A signal is generated by providing a clock signal having a frequency (f_osc). The clock frequency f_osc is arithmetically divided by an output frequency (f_o) associated with the signal to obtain a ratio R and a remainder given by x/y. The signal is derived from the clock signal by successively dividing the frequency (f_osc) of the clock signal by one of R and R+1, such that a fraction of times that the frequency (f_osc) of the clock signal is divided by R is given by 1-x/y and a fraction of times that the frequency (f_osc) of the clock signal is divided by R+1 is given by x/y. In particular, the signal is derived by driving a counter using the clock signal to a count value of one of R and R+1, such that a fraction of times that the counter is driven to a count value of R is given by 1-x/y and a fraction of times that the counter is driven to a count value of R+1 is given by x/y.