发明名称 |
Method and apparatus for decomposing a region of an integrated circuit layout |
摘要 |
Some embodiments of the invention provide a method of decomposing a region of an intergrated circuit ("IC") layout. The region contains several routable elements. Based on the routable elements, the method defines a plurality of nodes in the region. It then triangulates the region based on the nodes. The method then uses the triangles to define routes in the region.
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申请公布号 |
US7032201(B1) |
申请公布日期 |
2006.04.18 |
申请号 |
US20020230503 |
申请日期 |
2002.08.28 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
TEIG STEVEN;CALDWELL ANDREW |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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