| 摘要 |
At a time Tp when a wafer W is transferred into either a load lock chamber LL1 or LL2, periods PSL for the load lock chambers LL1 and LL2 to get ready to permit a transfer of a next wafer W thereinto are calculated based on a timing for exchange of wafers W between the load lock chamber LL1 or LL2 and a loader module LM. When the periods PSL are calculated, a loader arm LA1 or LA2 selects a next wafer W having the shortest period to get ready to be transferable into the load lock chamber LL1 or LL2, from load ports LP1 to LP3. This improves transfer delay in a cluster tool provided with the load lock chambers. <IMAGE> |
