| 摘要 |
A system and method for the static scheduling of test cases. A static scheduler is used to schedule the entire verification test of an integrated circuit in advance. The static scheduler is used in conjunction with a hardware description language (HDL) circuit design, a virtual test bench, and simulation software. The static scheduler is configured to assign test events to resources, or functional units, of the integrated circuit design. Events for a resource are assigned to available time slots, or cycles. During event scheduling, the static scheduler is configured to ensure that there are no resource conflicts for a given time slot. By scheduling all test events in advance, pitfalls associated with dynamic scheduling may be avoided, such as those associated with the use of semaphores. By avoiding the use of semaphores, complex test scenarios and boundary conditions may be more fully exercised, as resources will not be locked. This may allow a more thorough verification of an integrated circuit design.
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