发明名称 |
Method of designing semiconductor integrated circuit with accurate capacitance extraction |
摘要 |
A semiconductor integrated circuit includes a block having a first border edge on which an external connection terminal is provided and a second border edge on which no external connection terminal is provided, a wiring prohibited area which extends a first distance from the first border edge and in which no wiring line running parallel to the first border edge exists, and a shielding line which is at a second distance from the second border edge and runs parallel to the second border edge.
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申请公布号 |
US7032207(B2) |
申请公布日期 |
2006.04.18 |
申请号 |
US20040762277 |
申请日期 |
2004.01.23 |
申请人 |
FUJITSU LIMITED |
发明人 |
KUROSE SHINICHI;KUMAGAI KENJI |
分类号 |
G06F17/50;H01L21/82;H01L21/822;H01L27/00;H01L27/04 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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