| 摘要 |
A technique improves the performance of an integrated circuit design by selectively replacing low V<SUB>t </SUB>transistors with standard V<SUB>t </SUB>transistors. The selection of gates for replacement may be based on a multi-path timing analysis. If a low V<SUB>t </SUB>variant of a gate instance increases a path cycle time as compared to a standard V<SUB>t </SUB>counterpart, the maximum of the path cycle times for all paths that include the low V<SUB>t </SUB>variant and the maximum of the path cycle time for these paths with a standard V<SUB>t </SUB>variant are calculated. If the maximum path cycle time for the path including the low V<SUB>t </SUB>variant is greater than the maximum path cycle time for the path including the standard V<SUB>t </SUB>variant, then that low V<SUB>t </SUB>variant is substituted with a standard V<SUB>t </SUB>variant. Thus, integrated circuit designs prepared in accordance with the invention may exhibit improved cycle times.
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