| 摘要 |
An apparatus for performing data compression is disclosed. A circuit ( 640 ) within a comparison unit ( 400 ) of a comparison matrix ( 170 ) performs LZ1 compression of a data string by comparing bytes held in an input buffer ( 140 ) with bytes held in a history buffer ( 110, 120 ). A group of logic gate stages ( 720, 730, 740, 750 ) is connected in series with each other. Each of the logic gate stages produces a carry value that is passed to one of the output of the comparison unit and another logic gate stages. The product of the number stages in the logic gate stages and the number logic gates in each of the logic gate stages is less than the number of logic gates required for an equivalent circuit having a single logic circuit stage.
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