| 摘要 |
PROBLEM TO BE SOLVED: To provide a signal processing apparatus for a low-density parity check (LDPC) code for achieving a short arithmetic processing time in the case of employing software arithmetic operations and realizing a simple configuration at a low cost, even when employing a hardware circuit. SOLUTION: The signal processing apparatus for the low-density parity check code comprising: an encoder for the low-density parity check code for generating an N-bit code word by adding check bits (in M bits) to information bits (in K bits); and a decoder for decoding the information bits (in K bits) on the basis of the N-bit code word, and defines a generator matrix and a parity check matrix at the same time by using a partial matrix comprising powers of a square matrix, and a triangle matrix comprising the powers of the square matrix, a unit matrix, and a zero matrix. COPYRIGHT: (C)2006,JPO&NCIPI
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