<p>In one embodiment, a processing node includes a plurality of processor cores each including a cache memory coupled to a cache monitor unit and to a configuration unit. Each cache monitor unit may be configured to independently monitor a current utilization of the cache memory to which it is coupled and to determine whether the current utilization is below a predetermined utilization value. The configuration unit may selectably disable one or more portions of the cache memory in response to the cache monitor unit determining that the current utilization is below the predetermined utilization value.</p>
申请公布号
WO2006039153(A1)
申请公布日期
2006.04.13
申请号
WO2005US33671
申请日期
2005.09.21
申请人
ADVANCED MICRO DEVICES, INC.;GOLDEN, MICHAEL, L.;KLASS, RICHARD, E.