发明名称 CHIP PACKAGE STRUCTURE, PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF
摘要 A package substrate for carrying a chip with a plurality of bumps thereon is provided. The package substrate includes a first substrate, and an interposer. The first substrate has a first circuit layer disposed on a surface thereof. The interposer includes a second substrate and a second circuit layer formed thereon. The second circuit layer comprises a plurality of bonding pads and traces. The traces are electrically connected to the corresponding bonding pads. Furthermore, the bonding pads are used for being connected to the bumps. The second circuit layer of the interposer is physically and electrically connected to the first circuit layer of the first substrate, and the second substrate and the first substrate are made of different materials.
申请公布号 US2006076659(A1) 申请公布日期 2006.04.13
申请号 US20050163276 申请日期 2005.10.12
申请人 发明人 CHUNG CHIH-MING
分类号 H01L23/02;H01L21/56;H01L23/28 主分类号 H01L23/02
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