| 摘要 |
<p>In an information processor (100) shown in Fig. 2, one end of a data bus (30), which mutually connects a plurality of control calculation units (42) provided in a main processor (40), is connected with a graphic processor (10), and the other end is connected with a main memory (80). Image frame data generated by the graphic processor (10) is sequentially transmitted through the sequential data bus (30) to be stored in the main memory (80). When a rate of data transmission from the main processor (40) to the graphic processor (10) is R1, a rate of data transmission from the graphic processor (10) to the main processor (40) is R2, a rate of mutual data transmission between main processor (40) and the main memory (80) is R3 and a rate of transmitting data of one image frame within a vertical retrace time is R4, inequalities of R1=R2=R4 and R1=R3=R4 are satisfied.</p> |
