| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress reduction of an aperture while suppressing a voltage drop. <P>SOLUTION: A display panel comprises a transistor array board 50 having transistors 21 to 23 and a capacitor 24 per subpixel P as one dot. Scan lines X and supply lines Z in a horizontal direction as well as signal lines Y in a vertical direction are arranged on the transistor array board 50. Banks 71 parallel to the signal lines Y are projected on the surface of the board 50. A subpixel electrode 20a is provided between the banks 71, and the banks 71 and an organic EL layer 20b are laminated on the subpixel electrodes 20a. The organic EL layer 20b and the banks 71 are covered with an counter electrode 20c. Common wiring lines 91 are laminated on the counter electrode 20c so as to be overlapped therewith when viewed from top. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
