发明名称 System for format conversion using clock adjuster and method of the same
摘要 A system and same method are provided for producing video signal timing to a display apparatus that has different input/output image/video format. In addition to an image scaler, the system comprises a clock adjuster including a first and a second clock generator. The first clock generator generates a first clock signal by which the input/source pixel data included in the input/source image frame are received. The second clock signal is generated and adjusted to have an average clock period such that the ratio of the input and output frame rates is substantially kept constant. Thus, the skew between the source/input images and the display/output images can be adjusted, and the output frame repeating and/or dropping can be avoided.
申请公布号 US2006077288(A1) 申请公布日期 2006.04.13
申请号 US20040962727 申请日期 2004.10.12
申请人 WU JEN-SHI 发明人 WU JEN-SHI
分类号 G09G5/00;H04N7/01 主分类号 G09G5/00
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