发明名称 DATA PROCESSING SYSTEM WITH BUS ACCESS RETRACTION
摘要 <p>A bus master (12) may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter (216) may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.</p>
申请公布号 WO2006039040(A2) 申请公布日期 2006.04.13
申请号 WO2005US31115 申请日期 2005.09.01
申请人 FREESCALE SEMICONDUCTOR, INC.;MOYER, WILLIAM C.;GUMULJA, JIMMY;MURDOCK, BRETT W. 发明人 MOYER, WILLIAM C.;GUMULJA, JIMMY;MURDOCK, BRETT W.
分类号 G06F13/00 主分类号 G06F13/00
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