发明名称 INFORMATION PROCESSOR AND DATA TRANSFER CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To realize an information processor capable of realizing memory protection and efficiently using DMA transfer. SOLUTION: An I/O controller 130 connected with an I/O device 135 comprises a DMA controller (DMAC) 133 and an access control unit (ACU) 132. The DMAC 133 executes DMA transfer according to data transfer control information set to a control/status register 134 by a user process. The ACU 132 restricts the execution of DMA transfer by the DMAC 133 based on access control information set to a control/status register 131 by a privilege process to prohibit the access to memory areas other than a memory area to which the user process is accessible by the DMAC 133. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006099702(A) 申请公布日期 2006.04.13
申请号 JP20040288217 申请日期 2004.09.30
申请人 TOSHIBA CORP 发明人 HATAKEYAMA TETSUO
分类号 G06F13/28;G06F12/14 主分类号 G06F13/28
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