| 摘要 |
PROBLEM TO BE SOLVED: To suppress voltage drop and signal delay through wiring in a display panel that employs light-emitting elements as sub-pixels. SOLUTION: A display panel 1 is provided with a transistor array substrate 50 with transistors 21 to 23 and a capacitor 24 provided for a sub-pixel P of a single dot. Selection wiring 89 and feed wiring 90 are stacked on patterned scan lines X and supply lines Z, together with the drains/sources of the transistors 21 to 23. The selection wiring 89 is embedded in a protective insulating film 32 and a planarizing film 33 on the surface of the transistor array substrate 50. The feed wiring 90 is embedded in the protective insulating film 32 and the planarizing film 33 and is provided projectingly from the surface of the flat film 33. Sub-pixel electrodes 20a are arrayed in a matrix form on the surface of the flat film 33, and organic EL layers 20b are stacked on the sub-pixel electrodes 20a, and a counter electrode 20c is stacked on the organic EL layers 20b. COPYRIGHT: (C)2006,JPO&NCIPI
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