发明名称 METHOD OF ANALYZING FAULT OF SEMICONDUCTOR CHIP
摘要 PROBLEM TO BE SOLVED: To provide a method of analyzing the fault of semiconductor chip by which the fault distributing state of a plurality of semiconductor chips on a wafer can be analyzed without wasting nondefective chips. SOLUTION: The method of analyzing fault of semiconductor chip includes a first step of dicing the wafer 1 on which nondefective chips 2 and defective chips 3 are identified, and removing the nondefective chips 2 from the diced wafer 1; a second step of discriminating the positions of the left defective chips 3 on the wafer 1, storing first positional information (a and b) indicating the positions of the defective chips 3 on the wafer 1, and, at the same time, transferring the defective chips 3 to an analyzing stage 10 by picking up the chips 3. The method also includes a third step of preparing second positional information indicating the position of the fault in each defective chip 3, by analyzing the fault of each defective chip 3 on the analyzing stage 10, and identifying and displaying the defective chips 3 and the positions of the faults in the chips 3 on a wafer map 4 based on the prepared second positional information and stored first positional information (a and b). COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006100352(A) 申请公布日期 2006.04.13
申请号 JP20040281606 申请日期 2004.09.28
申请人 RENESAS TECHNOLOGY CORP 发明人 KOYAMA TORU;YOSHIDA TAKESHI
分类号 H01L21/66;G01R31/26 主分类号 H01L21/66
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