FAULT PROCESSING FOR DIRECT MEMORY ACCESS ADDRESS TRANSLATION
摘要
<p>An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.</p>
申请公布号
WO2006039177(A1)
申请公布日期
2006.04.13
申请号
WO2005US33933
申请日期
2005.09.21
申请人
INTEL CORPORATION;MADUKKARUMUKUMANA, RAJESH;SCHOINAS, IOANNIS;KING, KU-JEI;VEMBU, BALAJI;NEIGER, GILBERT;UHLIG, RICHARD
发明人
MADUKKARUMUKUMANA, RAJESH;SCHOINAS, IOANNIS;KING, KU-JEI;VEMBU, BALAJI;NEIGER, GILBERT;UHLIG, RICHARD