| 摘要 |
<p>Head capacitors are arranged in parallel between the input terminal and terminal of an integration capacitor connected to the output terminal of a filtering stage. The head capacitors are connected to the input terminals in successive clock cycles, and successive clock cycles are offset by one clock cycle from one filtering unit to the next one. Preferably the filter includes an arrangement for successively connecting each integration capacitor to the output terminal at the sampling frequency and for each filtering unit a decimation stage is connected to the output terminal of the filtering stage. Independent claims are also included for the following: (1) a cell receptor, such as a GSM cell receptor or a WCDMA cell receptor, comprising a filter according to the invention; (2) an electronic system; and (3) a method of filtering a discrete time signal formed by sequential samples.</p> |
