发明名称 Generation of mask-constrained floating-point addition and subtraction test cases, and method and system therefor
摘要 A method and system for generating numerical test cases for testing binary floating-point arithmetic units for addition and subtraction operations, in order to verify the proper operation of the units according to a specified standard. The space for eligible test-cases is compatible with masks which stipulate the allowable forms of the operands and the result, including constant as well as variable digits in both the exponent and significand fields. The test-cases, which are generated randomly, cover the entire solution space without excluding any eligible solutions. All standard rounding modes are supported, and if a valid solution does not exist for a given set of masks, this fact is reported. The method is general and can be applied to any standard, such as the IEEE floating-point standard, in any precision. A system according to the present invention utilizes a set of sub-generators for biased exponents and significands, and also incorporates a fixed-point generator for performing calculations common to the other generators. The method relies on searching for solutions based on feasible carry sequences, and is also capable of generating test-cases for mask-constrained carry sequences.
申请公布号 US7028067(B2) 申请公布日期 2006.04.11
申请号 US20020078111 申请日期 2002.02.20
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ABRAHAM ZIV;ASAF SIGAL;KOYFMAN ANATOLY;ZADOK SHAY
分类号 G06F11/263;G06F7/38 主分类号 G06F11/263
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