| 摘要 |
A shift register unit. The shift register unit outputs a shift register signal according to a clock signal, an inverse clock signal and a start signal. The shift register has first and second clock inversion circuits, and an inverter. In the first clock inversion circuit, a third PMOS transistor has a third source coupled to the first voltage, a third gate and a third drain. A fourth PMOS transistor has a fourth source coupled to the third drain, a fourth gate and a fourth drain coupled to the second voltage. A fifth PMOS transistor has a fifth source coupled to the third drain, a fifth drain coupled to the first gate, and a fifth gate. A sixth PMOS transistor having a sixth source coupled to the third gate, a sixth drain coupled to the second gate, and a sixth gate coupled to the fifth gate.
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