发明名称 |
Method for reducing defects in post passivation interconnect process |
摘要 |
A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer. |
申请公布号 |
US7026233(B2) |
申请公布日期 |
2006.04.11 |
申请号 |
US20030635621 |
申请日期 |
2003.08.06 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHENG HSI-KUEI;CHIEN HUNG-JU;CHAN HSUN-CHANG;CHEN CHU-CHANG;WANG YING-LANG;SU CHIN-HAO;FENG HSIEN-PING;CHANG SHIH-TZUNG |
分类号 |
H01L21/50;H01L21/44;H01L21/461;H01L21/4763;H01L21/60;H01L23/31;H01L23/485 |
主分类号 |
H01L21/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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