发明名称 |
Caching support for direct memory access address translation |
摘要 |
An embodiment of the present invention is a technique to provide cache support for direct memory access address translation. A cache structure stores cached entries used in address translation of a guest physical address to a host physical address. The guest physical address corresponds to a guest domain identified by a guest domain identifier in an input/output (I/O) transaction requested by an I/O device. A register stores an invalidating domain identifier identifying an invalidating domain and an indicator indicating invalidating an entry in the cached entries having a tag.
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申请公布号 |
US2006075147(A1) |
申请公布日期 |
2006.04.06 |
申请号 |
US20040956206 |
申请日期 |
2004.09.30 |
申请人 |
SCHOINAS IOANNIS;MADUKKARUMUKUMANA RAJESH;NEIGER GILBERT;UHLIG RICHARD;VEMBU BALAJI |
发明人 |
SCHOINAS IOANNIS;MADUKKARUMUKUMANA RAJESH;NEIGER GILBERT;UHLIG RICHARD;VEMBU BALAJI |
分类号 |
G06F3/00;G06F12/00;G06F13/28 |
主分类号 |
G06F3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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