| 摘要 |
In a chip package ( 10, 10', 110, 210 ), first and second electrical power buses ( 14, 14', 16, 16', 114, 116, 214, 216 ) are each formed of an electrical conductor having a chip bonding portion ( 20, 22, 120, 122, 220, 222 ) and a lead portion ( 26, 26', 28, 28', 126, 128, 226, 228 ) extending away from the chip bonding portion. The chip bonding portions of the first and second electrical power buses have edges ( 32, 34, 132, 134, 232, 234 ) spaced apart from one another to define an extended electrical isolation gap ( 40, 140, 240 ). A plurality of chips ( 42, 44, 46, 142, 143, 144, 145, 146, 147, 148, 242 ) straddle the extended electrical isolation gap and are electrically connected with the first and second electrical power buses to receive electrical power from the first and second electrical power buses. |
