发明名称 |
ASSERTION GENERATING SYSTEM, PROGRAM THEREOF, CIRCUIT VERIFYING SYSTEM, AND ASSERTION GENERATING METHOD |
摘要 |
<p>An assertion generating system is disclosed. In an assertion generating system 207, a graphical editor 201 generates design data of a semiconductor integrated circuit by graphically editing a specification (finite state machine, process sequence) of the semiconductor integrated circuit with the use of a state transition table and a state transition figure or by editing the process sequence into a timing chart and a time series figure based on user operations, and a syntax analyzer 203 and a property extractor 204 generate a property that verifies the specification of the semiconductor integrated circuit based on the design data. The assertion generator 205 converts the property into an assertion description language 206.</p> |
申请公布号 |
WO2006035854(A1) |
申请公布日期 |
2006.04.06 |
申请号 |
WO2005JP17921 |
申请日期 |
2005.09.21 |
申请人 |
RICOH COMPANY, LTD.;YAMADA, TAKAMITSU |
发明人 |
YAMADA, TAKAMITSU |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|