发明名称 |
Fault processing for direct memory access address translation |
摘要 |
An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.
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申请公布号 |
US2006075285(A1) |
申请公布日期 |
2006.04.06 |
申请号 |
US20040956630 |
申请日期 |
2004.09.30 |
申请人 |
MADUKKARUMUKUMANA RAJESH;SCHOINAS IOANNIS;KING KU-JEI;VEMBU BALAJI;NEIGER GILBERT;UHLIG RICHARD |
发明人 |
MADUKKARUMUKUMANA RAJESH;SCHOINAS IOANNIS;KING KU-JEI;VEMBU BALAJI;NEIGER GILBERT;UHLIG RICHARD |
分类号 |
G06F11/00 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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