Digital input signal collecting device, has memory control device disconnecting one memory over one chip-select-data link used for memories in clock cycle by releasing signal or disconnecting data bus driver device by one of remaining links

摘要

The device has a control device (1) receiving an adjusted input signal over a data bus (2) and generating an output signal for controlling a coupled device by the received input signal. A memory control device (7) disconnects one of memories over one of chip-select-data links used for the memories in a clock cycle by a releasing signal or disconnects a data bus driver device (5) by one of the remaining chip-select-data links.