STRUCTURALLY-ENHANCED INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURE
摘要
A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free form encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.
申请公布号
WO2006035321(A2)
申请公布日期
2006.04.06
申请号
WO2005IB03992
申请日期
2005.05.05
申请人
UNITED TEST AND ASSEMBLY CENTER, LTD.;KOLAN, RAVI, KANTH;TAN, HIEN, BOON;SUN, YI-SHENG, ANTHONY;KUAN, LIM, BENG;SHIVALINGAM, KRISHNAMURTHY