Data synchronization arrangement

摘要

The data synchronization device uses a buffer memory (12) with a defined limited number of memory locations, associated with a write-in selection multiplexer (10) and a read-out selection multiplexer (14), for write-in and read-out of data to and from the memory locations. The write-in selection multiplexer and the read-out selection multiplexer are operated in synchronization with a clock (WR-CLOCK) of a first clock region and a clock (RD-CLOCK) of a second clock region respectively, using a write-in selection shift register (16) and a read-out selection shift register (18).