发明名称 Integrated circuit for generating a plurality of direct current (DC) output voltages
摘要 A cascaded DC-DC converter architecture has an upstream converter stage and a downstream converter stage, which derives its input voltage from the upstream stage. Cascading the two converter stages enables functionality of control and monitoring (including soft start and overcurrent detection) circuitry of the upstream stage to be used for the downstream stage, to reduce chip area, cost, and complexity. A voltage window regulator in the downstream converter ensures that, during shutdown, its output voltage will be maintained within a prescribed window of its regulated output voltage, so that no soft start delay is needed when the second converter stage is turned back on.
申请公布号 US7023187(B2) 申请公布日期 2006.04.04
申请号 US20020213766 申请日期 2002.08.07
申请人 INTERSIL AMERICAS INC. 发明人 SHEARON WILLIAM B.;SFERRAZZA PAUL K.
分类号 H02M3/158 主分类号 H02M3/158
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