发明名称 |
Memory cell structure |
摘要 |
A memory structure that reduces soft-errors for us in CMOS devices is provided. The memory cell layout utilizes transistors oriented such that the source-to-drain axis is parallel a shorted side of the memory cell. The dimensions of the memory cell are such that it has a longer side and a shorter side, wherein the longer side is preferably about twice as long as the shorter side. Such an arrangement uses a shorter well path to reduce the resistance between transistors and the well strap. The shorter well strap reduces the voltage during operation and soft errors.
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申请公布号 |
US7023056(B2) |
申请公布日期 |
2006.04.04 |
申请号 |
US20030723331 |
申请日期 |
2003.11.26 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LIAW JHON-JHY |
分类号 |
H01L29/76;G11C11/34;G11C11/412;G11C16/04;H01L21/8234;H01L21/8244;H01L27/092;H01L27/10;H01L27/11;H01L29/78;H01L29/94;H01L31/062;H01L31/113;H01L31/119 |
主分类号 |
H01L29/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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