发明名称 Processor multiple function units executing cycle specifying variable length instruction block and using common target block address updated pointers
摘要 A multiprocessor data processing system for executing a program having branch instructions therein, each branch instruction specifying a target address in the program defining an instruction that is to be executed if that branch instruction causes the program to branch. The data processing system includes a plurality of processing sections having a function unit, a local memory, and a pointer. The local memory stores instruction sequences from the program that is to be executed by the function unit in that processing section. The pointer contains a value defining the next instruction in the local memory to be executed by the function unit. Each function unit executes instructions according to machine cycles, each function unit executing one instruction per machine cycle. The pointers in each of the processing sections are reset to a new value determined by the target address of one of the branch instructions when a function unit branches in response to that branch instruction.
申请公布号 US7024538(B2) 申请公布日期 2006.04.04
申请号 US20010032177 申请日期 2001.12.21
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 SCHLANSKER MICHAEL STEVEN
分类号 G06F9/40;G06F9/32;G06F9/38 主分类号 G06F9/40
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