发明名称 Semiconductor package structure with reduced parasite capacitance and method of fabricating the same
摘要 A semiconductor package structure for improving electrical performance and a method for fabricating the same are proposed, in which a substrate having at least one pair of passive component pads is provided, wherein a semiconductor chip is attached on the substrate and a passive component is mounted to the passive component pads to locate between the substrate and the semiconductor chip. Thus, the passive component can electrically connect the chip and the substrate simultaneously without arranging an additional conductive trace layer, thereby improving the electrical performance of the semiconductor package structure and reducing the structure size.
申请公布号 US7023085(B2) 申请公布日期 2006.04.04
申请号 US20040921582 申请日期 2004.08.18
申请人 SILICONWARE PRECISION INDUSTRIES CO., LTD 发明人 PU HAN-PING
分类号 H01L23/34;H01L21/60;H01L23/04;H01L23/64 主分类号 H01L23/34
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